This invention relates to semiconductor devices, and more particularly to static column decode circuits for semiconductor dynamic memory devices.
Dynamic MOS read/write memory devices have been constructed generally as shown in U.S. Pat. No. 4,081,701 (a 16K dynamic ROM) issued to White, McAdams and Redwine, or U.S. Pat. No. 4,239,993 (a 64K dynamic RAM) issued to McAlexander, White and Rao, both assigned to Texas Instruments. In each of these prior devices a cell array which was .sqroot.N on a side was used, where N is the number of cells. Thus, a 64K device had 256 rows and 256 columns. A bistable sense amplifier was connected to a pair of bit lines; there was one sense amplifier for each column, each column having two bit lines. In these square arrays, the refresh cycle was equal to the number of column lines, or the number of sense amplifiers. However, when the bit density of a dynamic RAM increases to levels such as 256K-bits or 1-Megabit, the number of sense amplifiers must be increased beyond .sqroot.N (where N is the total number of bits), because the number of cells per bit line cannot exceed about 128 due to capacitance ratios and series resistance, and the refresh cycle must not exceed about 256 or 512-per refresh period.
To provide a 256 cycle refresh in a 1-Megabit DRAM, the number of columns must be 4096 in a simple array, i.e., 256 rows by 4096 columns. By addressing two rows per refresh cycle, this can be reduced to a 512.times.2048 array. Even so, the number of columns coupled to a given I/O or I/O data path in this case would be entirely too large due to the parasitic capacitance of such a number of column lines. When static column decoding is included, the circuit design becomes more difficult.
It is the principal object of this invention to provide a data input/output arrangement for a high density dynamic RAM. Another object is to provide high speed data I/O circuitry for a dynamic RAM.